![]() The firmware + GPIF has been modified to use GPIF's addressing lines and MultiChannel DMA to alternate data between threads 0 and 1 so when a thread is emptying the other is used (like ping-pong buffers) to improve throughput. It writes until it sees the watermark assert (configured to assert when >=15372 bytes are received). These packets are sent to the USB host on PKTEND assertion or when the buffer is full at 16KB-16 bytes. ![]() The FPGA increments the counter with every write to GPIF and writes to GPIF in bursts of 253 words. The data is a 32-bit word with 28-bits as a counter and 4 1-bit flags. ![]() I have an FPGA feeding uncompressed counter data into the 32-bit GPIF bus using the AN65974 Slave FIFO state machine.
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